The present invention relates to a signal transmitting device in a semiconductor apparatus, and more particularly to improvements in a signal transmitting system having a large number of gate stages, for example a signal transmitting device having an additional circuit such as a noise removing circuit or the like for assuring a predetermined normal function.
Conventionally, there is known a semiconductor apparatus having a signal transmitting system in which the number of gate stages is increased because of provision of a large number of logical elements, e.g., a signal transmitting system having an additional circuit such as a noise removing circuit or the like to prevent an erroneous operation due to noise in an input signal such that a normal function is assured.
With reference to FIG. 3, the following description will discuss, in the form of an output gate control circuit of a DRAM, a signal transmitting device in a conventional semiconductor apparatus having a noise removing circuit as an additional circuit.
In FIG. 3, a /CAS (Column Address Strobe) input circuit 1 is simplified as formed by an inverter. An output from the inverter 1 is turned into a signal 2, which is in an activated state at "H" and in an inactivated state at "L".
The signal 2 is entered into a noise removing circuit 80 which is formed by inverters 3, 5, 6 and a NAND circuit 8. In the noise removing circuit 80, the signal 2 is entered into the inverter 3, which supplies a signal 4. The signal 4 is delayed by the inverters 5, 6 and the inverter 6 generates a signal 7. The signals 4, 7 are entered into the NAND circuit 8, which generates a signal 9. The signal 9 is an output of the noise removing circuit 80. More specifically, even though the signal 4 becomes "H" due to momentary entry of reset noise into the signal 2 which is in the activated state, the signal 7 is held at "L" such that the signal 9 remains unchanged in the state "H", thus removing the noise.
The signal 9 from the noise removing circuit 80 is entered into a latch 81 which comprises a flip-flop circuit formed by two NAND circuits 10, 11. The signal 9 is entered into the NAND circuit 10. The NAND circuit 10 supplies a signal 12, which is then entered into the NAND circuit 11. A signal 13 from the NAND circuit 11 is entered into the other NAND circuit 10.
The signal 2 is delayed by inverters 14, 15, 16, and the inverter 16 generates a signal 17. A /WE (Write Enable) input circuit 18 is formed by an inverter and supplies an output signal 19. The signal 19 passes through an inverter 20, which inverts the signal 19 into a signal 21. The signals 17 and 21 are entered into a NAND circuit 22, which generates a signal 23. This signal 23 is entered into the NAND circuit 11 of the latch 81. The state of the signal 23 is latched by the latch 81.
The signal 12 from the latch 81 passes through an inverter 24, which inverts the signal 12 into a signal 25. An /OE (Output Enable) input circuit 26 is formed by an inverter and generates a signal 27. The signals 25, 27 are entered into a NAND circuit 28, which generates a signal 29. The signal 29 is a signal as obtained by latching the signal 23 from the NAND circuit 22.
The signal 29 passes through an inverter 51, which inverts the signal 29 into a signal 42. An output buffer circuit 43 is activated when the signal 42 is activated. The output buffer circuit 43 comprises: two NAND circuits 44, 45 to which the signal 42 and data are entered; an inverter 46 for inverting the data and giving a data inverting signal to the NAND circuit 45; an inverter 47 for inverting an output signal of the NAND circuit 45; and output transistors 48, 49. The output buffer circuit 43 supplies a signal 50.
The following description will discuss the roles and operations of the terminals of the DRAM. In the DRAM, a /CAS terminal is used for latching a column address and for controlling an output. A /WE terminal is used for determining an operation, either a reading or writing operation, to be conducted by the DRAM. More specifically, when the /WE terminal is in the state "H", a reading operation is carried out, and when the /WE terminal is in the state "L", a writing operation is carried out. However, the DRAM is arranged such that, when the /WE terminal is in the state "L" at the time the /CAS terminal is changed in state from "H" to "L", the state where the /WE terminal is in the state "L", is latched such that no data are supplied even though the /WE terminal is changed in state to "H" after the /CAS terminal has been changed from "H" to "L". This operation is called an early write mode. On the contrary, when the /WE terminal is in the state "H" at the time the /CAS terminal is changed in state from "H" to "L", a reading operation is conducted. However, if the /WE terminal is changed in state to "L" thereafter, the operation mode is immediately changed to a writing operation. More specifically, the state where that the /WE terminal is in the state "H", is not latched. In this case, writing is carried out while data are being read. Accordingly, when a data input terminal is identical with a data output terminal, data to be written and data to be read interfere with each other. In this connection, the DRAM has an /OE terminal which determines whether or not data is supplied. The DRAM is arranged such that no data is supplied when the /OE terminal is in the state "H", and data is supplied when the /OE terminal is in the state "L". More specifically, when the /CAS terminal is changed in state from "H" to "L" with the /WE terminal being in the state "H", a reading operation is carried out, but data can be supplied only when the /OE terminal is in the state "L". To conduct a writing operation thereafter, it is required that the /WE terminal is changed in state from "H" to "L" after the /OE terminal has been changed in state from "L" to "H" to stop data output. This operation is called delayed write or /OE controlled write. Also, there is an operation which validates both data output at the time of reading and data input at the time of writing. This operation is particularly called read modify write. For this operation, there are determined standards as to timing of an input signal to be given for transferring a reading operation to a writing operation.
The operations above-mentioned will be discussed in the form of operations conducted inside of the circuit in FIG. 3.
When the DRAM stands ready, the signal 2 becomes the state "L" since the /CAS terminal is in the state "H". Then, the signal 4 is in the state "H", the signal 9 is in the state "L", the signal 12 is in the state "H", the signal 25 is in the state "L", the signal 29 is in the state "H" and the signal 42 is in the state "L". Thus, no output is supplied.
The following description will discuss the reading operation also referring to a timing chart shown in FIG. 4. In this reading operation, the /CAS terminal is changed in state from "H" to "L" with the /WE terminal being in the state "H". Accordingly, when the /CAS terminal is in the state "H", the signal 23 is in the state "L" and the signal 13 is in the state "H". At this time, the /OE terminal is in the state "L" and the signal 27 is in the state "H". In this state, when the /CAS terminal is changed in state from "H" to "L", the signal 2 becomes the state "H" and the signal 9 becomes the state "H". Since the signal 13 is in the state "H", the signal 12 becomes the state "L" and the signal 13 is latched as "H". Here, even though reset noise mixingly enters the signal 2, the signal 9 is held at the state "H" by the noise removing circuit 80 and the output signal 12 of the NAND circuit 10 is held at the state "L". Accordingly, the signal 13 is continuously latched at "H". Thereafter, the signal 17 becomes the state "L" and the signal 23 becomes the state "H" as delayed by a predetermined period of time. Thereafter, since the signal 25 becomes the state "H" and the signal 27 becomes the state "H", the signal 29 becomes the state "L" and the signal 42 becomes the state "H", thus causing the output buffer circuit 43 to be activated. Accordingly, in the output buffer circuit 43, when the signal 42 is in the state "H", the output transistor 48 is activated to turn the output 50 into the state "H" when data is in the state "H", and the output transistor 49 is activated to turn the output 50 into the state "L" when the data is in the state "L".
Here, when the /WE terminal is changed from the state "H" to the state "L", the signal 21 becomes the state "L". However, since the signal 17 is already in the state "L", the signal 23 remains unchanged in the state "H". Accordingly, the states of the subsequent signals remain unchanged and the output buffer circuit 43 remains in the activated state so that the output 50 undergoes no change.
The following will discuss the case when there is not disposed the noise removing circuit 80 shown in FIG. 3. As shown in FIG. 5, when noise which is momentarily turned to "H", is entered at the time when the /CAS terminal is in the state "L", the signal 2 momentarily becomes the state "L". This signal 2 is entered, as it is as the signal 9, into the NAND circuit 10 of the latch 81, and the signal 12 momentarily becomes the state "H". Since the signal 23 is already in the state "H", the signal 13 becomes the state "L". Accordingly, even though the signal 9 is returned to the state "H", the signal 12 is latched as in the state "H" because the signal 13 is in the state "L". As a result, the signal 29 becomes the state "H" and the output buffer circuit 43 is inactivated so that the output 50 is not supplied. However, when the noise removing circuit 80 is disposed, it is possible to prevent the output buffer circuit 43 from being inactivated due to noise at the time of a reading operation. This prevents such an erroneous operation as to stop the output 50.
The following will discuss a writing operation in the form of an early write operation where the /CAS terminal is changed from the state "H" to the state "L" with the /WE terminal being in the state "L". It is considered that the circuit stands ready immediately before the /CAS terminal is changed from the state "H" to the state "L". Further, the signal 21 from the /WE terminal is in the state "L". Accordingly, the signal 23 becomes the state "H". Further, since the signal 12 is in the state "H", the signal 13 is in the state "L". Here, when the /CAS terminal is changed from the state "H" to the state "L", the signal 2 is activated as changed from the state "L" to the state "H", and the signal 9 becomes the state "H". However, since the signal 13 is in the state "L", the signal 12 remains unchanged in the state "H". Thereafter, even though the signal 17 is changed from the state "H" to the state "L" after a predetermined delay time from the point of time that the signal 2 is activated, the signal 21 form the /WE terminal is in the state "L". Accordingly, the signal 23 remains unchanged in the state "H". As mentioned earlier, since the signals 12, 23 remain unchanged in the state "H", the signal 13 remains in the state "L". Accordingly, the states of the subsequent signals remain in the waiting states above-mentioned. That is, since the signal 42 becomes the state "L", the output buffer circuit 43 is inactivated so that the output 50 is not supplied.
Then, when the /WE terminal is returned from the state "L" to the state "H", the signal 21 is changed from the state "L" to the state "H". However, since the signal 17 is in the state "L", the signal 23 remains unchanged and the signal 42 remains in the state "L". Therefore, the output buffer circuit 43 is not activated so that the output 50 is still not supplied.
However, a semiconductor apparatus having such a conventional signal transmitting system having a large number of gate stages, presents the following problem. That is, because of a large number of gate stages, it takes much time to activate a signal to be ultimately supplied from the signal transmitting system, thus lowering the operation in speed.
The problem above-mentioned will be specifically discussed with reference to the arrangement of a semiconductor apparatus having the conventional noise removing circuit shown in FIG. 3. In the circuit in FIG. 3, between the point of time that the /CAS terminal is turned to the state "L" to activate the signal 2 and the point of time that the signal 29 is activated, there are six-stage gates including the inverter 1, the inverter 3, the NAND circuit 8, the NAND circuit 10, the inverter 24 and the NAND circuit 28. Thus, it takes time before the signal 29 is activated.
If the noise removing circuit 80 is taken away, the number of the gate stages can be reduced to four stages to increase the signal transmission in speed. However, without a noise removing circuit, the signal transmitting system cannot perfectly resist against noise. Thus, such a noise removing circuit cannot be taken away.